LC or RC matching of networks is critical for some analog or RF circuits. Adjustment of capacitor values after the circuits are already in use is not possible. Once the capacitor value has been pre-set, subsequent fine tuning is not possible and an entirely new mask is needed for the capacitor portions of the circuit. Additionally, conventional flat capacitor designs tend to occupy large amounts of chip real estate, acting as a bottleneck for further circuit densification.
In the pre-integrated circuit era, one of the ways of providing an adjustable capacitor was the layout schematically shown in FIG. 1. Seen there are four top electrodes 15 that share a common lower electrode 11. By means of switches 16 the top electrodes can be connected in parallel, as needed to provide a capacitance value between 1 and 9 units between points A and B since, as can be seen, the ratios of the individual top electrode areas are 5:2:1:1.
The present invention discloses how the schematic circuit of FIG. 1 can be implemented in an integrated circuit, with minimum consumption of chip real estate.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 5,350,705, Brassington et al. show a flat capacitor arrangement with common top plate. Aitken et al. in U.S. Pat. No. 6,088,258 shows a planarized interweave capacitor. In U.S. Pat. No. 5,604,145, Hashizume et al. disclose a planar capacitor process while in U.S. Pat. No. 5,744,385, Bojabri reveals a compensation technique for a parasitic capacitor.